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cy7c185 64-kbit (8 k 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05043 rev. *e revised april 20, 2011 features high speed ? 15 ns fast t doe low active power ? 715 mw low standby power ? 85 mw cmos for optimum speed/power easy memory expansion with ce 1 , ce 2 and oe features ttl-compatible inputs and outputs automatic power-down when deselected available in non pb-free 28-pin (300-mil) molded soj, 28-pin (300-mil) molded soic and pb-free 28-pin (300-mil) molded dip functional description the cy7c185 [1] is a high-performance cmos static ram organized as 8192 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce 1 ), an active high chip enable (ce 2 ), and active low output enable (oe ) and tri-state drivers. this device has an automatic power-down feature (ce 1 or ce 2 ), reducing the power consumption by 70% when deselected. the cy7c185 is in a standard 300-mil-wide dip, soj, or soic package. an active low write enable signal (we ) controls the writing/reading operation of the memory. when ce 1 and we inputs are both low and ce 2 is high, data on the eight data input/output pins (i/o 0 through i/o 7 ) is written in to the memory location addressed by the address present on the address pins (a 0 through a 12 ). reading the device is accomplished by selecting the device and enabling the outputs, ce 1 and oe active low, ce 2 active high, while we remains inactive or high. under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input or output pins. the input or output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (we ) is high. a die coat is used to insure alpha immunity. a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 0 a 10 a 9 a 11 a 12 i/o 0 8k x 8 array input buffer column decoder row decoder sense amps power down i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ce 1 ce 2 we oe logic block diagram selection guide description -15 -20 -35 maximum access time (ns) 15 20 35 maximum operati ng current (ma) 130 110 100 maximum cmos standby current (ma) 15 15 15 note 1. for guidelines on sram system design, please refer to the ?s ystem design guidelines? cypress application note, available on t he internet at www.cypress.com . [+] feedback
cy7c185 document #: 38-05043 rev. *e page 2 of 15 contents pin configuration ............................................................. 3 maximum ratings ............................................................. 3 operating range ............................................................... 3 electrical characteristics ................................................. 3 capacitance ...................................................................... 4 switching characteristics ,over the operating range ................................................. 5 switching waveforms ...................................................... 6 typical dc and ac characteristics ................................ 9 truth table ...................................................................... 10 address designators ..................................................... 10 ordering information ...................................................... 10 ordering code definitions ..... .................................... 10 package diagrams .......................................................... 11 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 document history page ................................................. 14 sales, solutions, and legal information ...................... 15 worldwide sales and design s upport ......... .............. 15 products .................................................................... 15 psoc solutions ......................................................... 15 [+] feedback
cy7c185 document #: 38-05043 rev. *e page 3 of 15 pin configuration maximum ratings exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature .................................. ?65 c to +150 c ambient temperature with power applied ............................................. ?55 c to +125 c supply voltage to ground potenti al ...............?0.5 v to +7.0 v dc voltage applied to outputs in high z state [2] ...........................................?0.5 v to +7.0 v dc input voltage [2] ........................................?0.5 v to +7.0 v output current into outputs (low) .............................. 20 ma static discharge voltage........................................... >2001 v (per mil-std-883, method 3015) latch-up current ..................................................... >200 ma 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc we ce 2 a 3 a 2 a 1 oe a 0 ce 1 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 nc a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 i/o 0 i/o 1 i/o 2 gnd top view dip/soj operating range range ambient temperature v cc commercial 0 c to +70 c 5 v 10% industrial ?40 c to +85 c 5 v 10% electrical characteristics over the operating range parameter description test conditions ?15 ?20 ?35 unit min max min max min max v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3 v 2.2 v cc + 0.3 v 2.2 v cc + 0.3 v v v il input low voltage [2] ?0.5 0.8 ?0.5 0.8 ?0.5 0.8 v i ix input leakage current gnd v i v cc ?5 +5 ?5 +5 ?5 +5 a i oz output leakage current gnd v i v cc , output disabled ?5 +5 ?5 +5 ?5 +5 a i cc v cc operating supply current v cc = max., i out = 0 ma 130 110 100 ma i sb1 automatic power-down current max. v cc , ce 1 v ih or ce 2 v il min. duty cycle =100% 40 20 20 ma i sb2 automatic power-down current max. v cc , ce 1 v cc ? 0.3 v, or ce 2 0.3 v v in v cc ? 0.3 v or v in 0.3 v 15 15 15 ma [+] feedback
cy7c185 document #: 38-05043 rev. *e page 4 of 15 capacitance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0 v 7 pf c out output capacitance 7 pf figure 1. ac test loads and waveforms r1 481 3.0 v 5 v output r1 481 r2 255 30 pf gnd 90% 90% 10% 5ns 5 ns 5 v output r2 255 5 pf (a) (b) output 1.73 v including jig and scope including jigand scope 10% equivalent to: thvenin equivalent all input pulses 167 2. minimum voltage is equal to ?3.0 v for pulse durations less than 30 ns. 3. tested initially and after any design or proce ss changes that may affect these parameters. [+] feedback
cy7c185 document #: 38-05043 rev. *e page 5 of 15 switching characteristics over the operating range [4] parameter description -15 -20 -35 unit min max min max min max read cycle t rc read cycle time 15 20 35 ns t aa address to data valid 15 20 35 ns t oha data hold from address change 3 5 5 ns t ace1 ce 1 low to data valid 15 20 35 ns t ace2 ce 2 high to data valid 15 20 35 ns t doe oe low to data valid 8 9 15 ns t lzoe oe low to low z 3 3 3 ns t hzoe oe high to high z [5] 7 8 10 ns t lzce1 ce 1 low to low z [6] 3 5 5 ns t lzce2 ce 2 high to low z 3 3 3 ns t hzce ce 1 high to high z [5, 6] ce 2 low to high z 7 8 10 ns t pu ce 1 low to power-up ce 2 to high to power-up 0 0 0 ns t pd ce 1 high to power-down ce 2 low to power-down 15 20 20 ns write cycle [7] t wc write cycle time 15 20 35 ns t sce1 ce 1 low to write end 12 15 20 ns t sce2 ce 2 high to write end 12 15 20 ns t aw address setup to write end 12 15 25 ns t ha address hold from write end 0 0 0 ns t sa address setup to write start 0 0 0 ns t pwe we pulse width 12 15 20 ns t sd data setup to write end 8 10 12 ns t hd data hold from write end 0 0 0 ns t hzwe we low to high z [5] 7 7 8 ns t lzwe we high to low z 3 5 5 ns notes 4. test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 5. t hzoe, t hzce , and t hzwe are specified with c l = 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady state voltage. 6. at any temperature and voltage condition, t hzce is less than t lzce1 and t lzce2 for any given device. 7. the internal write time of the memory is defined by the overlap of ce 1 low, ce 2 high, and we low. all 3 signals must be active to initiate a write and either signal can terminate a write by going high. the data input setup and hold timing must be referenced to the rising edge of the signal t hat terminates the write. [+] feedback
cy7c185 document #: 38-05043 rev. *e page 6 of 15 switching waveforms figure 2. read cycle no.1 [8,9] figure 3. read cycle no.2 [10,11] address data out previous data valid data valid t rc t aa t oha 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance impedance icc isb t hzoe t hzce t pd oe high data out v cc supply current ce 1 oe ce 2 notes 8. device is continuously selected. oe , ce 1 = v il . ce 2 = v ih . 9. we is high for read cycle. 10. data i/o is high z if oe = v ih , ce 1 = v ih , we = v il , or ce 2 =v il . 11. the internal write time of the memory is defined by the overlap of ce 1 low, ce 2 high and we low. ce 1 and we must be low and ce 2 must be high to initiate write. a write can be terminated by ce 1 or we going high or ce 2 going low. the data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write. [+] feedback
cy7c185 document #: 38-05043 rev. *e page 7 of 15 figure 4. write cycle no. 1 (we controlled) [9,11] figure 5. write cycle no. 2 (ce controlled) [11,12,13] notes 12. during this period, the i/os are in the output state and input signals must not be applied. 13. the minimum write cycle time for write cycle #3 (we controlled, oe low) is the sum of t hzwe and t sd . switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc t hzoe data in valid ce ce 1 oe we ce 2 data i/o t scei t sce2 address note 12 t wc t aw t sa t ha t hd t sd t sce1 we data i/o address ce 1 data in valid t sce2 ce 2 [+] feedback
cy7c185 document #: 38-05043 rev. *e page 8 of 15 figure 6. write cycle no. 3 (we controlled, oe low) [11,12,13,14] note 14. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in a high-impedance state. switching waveforms (continued) t hd t sd t lzwe t sa t ha t aw t wc t hzwe data in valid t sce1 t sce2 ce 1 ce 2 address data i/o we note 12 [+] feedback
cy7c185 document #: 38-05043 rev. *e page 9 of 15 typical dc and ac characteristics ?55 25 125 1.2 1.0 0.8 output source current (ma) ambient temperature ( c) 0.6 0.4 0.2 0.0 normalized i, i cc i sb v cc =5.0 v v in =5.0 v i cc sb 1.2 1.4 1.0 0.6 0.4 0.2 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0 0.8 ?55 25 125 normalized t aa 120 100 80 60 40 20 0.0 1.0 2.0 3.0 4.0 supply voltage (v) normalized supply current vs. supply voltage normalized access time vs. ambient temperature ambient temperature ( c) normalized supply current vs. ambient temperature output voltage (v) output source current vs. output voltage 0.0 0.8 1.4 1.3 1.2 1.1 1.0 0.9 4.0 4.5 5.0 5.5 6.0 normalized t aa supply voltage (v) normalized access time vs. supply voltage 120 140 100 60 40 20 0.0 1.0 2.0 3.0 4.0 output sink current (ma) 0 80 output voltage (v) output sink current vs. output voltage normalized i, i cc sb i cc v cc =5.0 v v cc =5.0 v t a =25 c v cc =5.0 v t a =25 c i sb t a =25 c 0.6 0.8 0 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.0 2.0 3.0 4.0 normalized i po supply voltage (v) typical power-on current vs. supply voltage 30.0 25.0 20.0 15.0 10.0 5.0 0 200 400 600 800 delta t (ns) aa capacitance (pf) typical access time change vs. output loading 1.25 1.00 0.75 10 20 30 40 normalized i cc cycle frequency (mhz) normalized i cc vs. cycle time 0.0 5.0 0.0 1000 0.50 v cc =4.5 v t a =25 c v cc =5.0 v t a =25 c v cc =0.5 v [+] feedback
cy7c185 document #: 38-05043 rev. *e page 10 of 15 truth table ce 1 ce 2 we oe input/out- put mode h x x x high z deselect/ power-down x l x x high z deselect/ power-down l h h l data out read l h l x data in write l h h h high z deselect address designators address name address function pin number a4 x3 2 a5 x4 3 a6 x5 4 a7 x6 5 a8 x7 6 a9 y1 7 a10 y4 8 a11 y3 9 a12 y0 10 a0 y2 21 a1 x0 23 a2 x1 24 a3 x2 25 ordering information speed (ns) ordering code package name package type operating range 15 cy7c185-15vi 51-85031 28-pin (300-mil) molded soj industrial 20 cy7c185-20pxc 51-85014 28-pin (300-mil) molded dip (pb-free) commercial 35 CY7C185-35SC 51-85026 28-pin (300-mil) molded soic commercial ordering code definitions temperature range: x = c or i c = commercial; i = industrial package type: xx = v or px or s v = 28-pin molded soj px = 28-pin molded dip (pb-free) s = 28-pin molded soic speed: 15 ns or 20 ns or 35 ns 85 = 64 kbit density with datawidth 8 bits 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 - xx xx 7 85 x [+] feedback
cy7c185 document #: 38-05043 rev. *e page 11 of 15 package diagrams figure 7. 28-pin (300-mil) pdip (51-85014) figure 8. 28-pin (300-mil) molded soic (51-85026) 51-85014 *e 51-85026 *f [+] feedback
cy7c185 document #: 38-05043 rev. *e page 12 of 15 figure 9. 28-pin (300-mil) molded soj (51-85031) package diagrams (continued) 51-85031 *d [+] feedback
cy7c185 document #: 38-05043 rev. *e page 13 of 15 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory soj small outline j-lead tsop thin small outline package vfbga very fine-pitch ball grid array symbol unit of measure ns nano seconds vvolts a micro amperes ma milli amperes mv milli volts mw milli watts mhz mega hertz pf pico farad c degree celcius wwatts [+] feedback
cy7c185 document #: 38-05043 rev. *e page 14 of 15 document history page document title: cy7c185, 64-kbit (8 k 8) static ram document number: 38-05043 revision ecn submission date orig. of change description of change ** 107145 09/10/01 szv change from spec number: 38-00037 to 38-05043 *a 116470 09/16/02 cea add applicat ions foot note to data sheet *b 486744 see ecn nxr changed low standby power from 220mw to 85mw changed the description of i ix from input load current to input leakage current in dc electrical characteristics table removed i os parameter from dc electrical characteristics table updated the ordering information table *c 2263686 see ecn vkn/aesa re moved 25 ns speed bin updated the ordering information table as per the current product offerings *d 3105329 12/09/2010 aju added ordering code definitions . updated package diagrams . *e 3235800 04/20/2011 pras template changes. added acronyms and units of measure. updated package diagram spec 51-85026 to *f. [+] feedback
document #: 38-05043 rev. *e revised april 20, 2011 page 15 of 15 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c185 ? cypress semiconductor corporation, 2001-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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